Mask Designer - 608301
2011-Aug-17
Freshers
Bengaluru/ Bangalore
2012-Aug-17
Freshers
Bengaluru/ Bangalore
2012-Aug-17
Job Details:
Creates bottoms-up elements of chip design including but not limited to: FET, cell, and block-level custom layouts, FUB-level floor plans, abstract view generation, RC extraction, and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, packaging, and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing, execution, and verification of complex chips development and execution of project methodologies and/or flow developments.
Candidate Profile:
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